The present invention is directed to an efficient method and architecture that performs both decimation and channel filtering for complex signals, and more particularly to a communication device capable of decimation and channel filtering using the same architecture for both functions.
To achieve optimal static, simulcast, and fading performance in a wireless receiver, a multi-bit digital detector such as a correlator based demodulator is typically required. A sufficient number of bits of dynamic range must be provided at the input of such a type of detector to achieve this. Thus, an analog-to-digital (A/D) conversion needs to be performed at a particular point in the receiver signal path to provide the desired number of bits of resolution at the detector. In the latest technology, one of the most cost and power efficient ways to provide a large dynamic range is to use a 1-bit oversampled sigma delta AID converter. However, to convert from the high oversampled rate of the sigma delta converter to the much lower baseband sampling rate while trying to preserve the in-band signal-to-noise ratio, a decimation filter is required. In addition, following the decimation filter, a channel filter is typically needed in a wireless receiver to sufficiently attenuate interfering adjacent channel signals before digital detection can be performed. Currently, there are no low cost power efficient architectures to provide both decimation and channel filtering. Thus, what is needed is a very low cost and power efficient hardware architecture to perform both decimation as well as channel filtering using the same basic architecture.